This invention relates generally to semiconductor packaging. More specifically this invention relates to a method for fabricating semiconductor packages using a mold tooling fixture with flash control cavities.
One type of semiconductor package is referred to as a BGA package. BGA packages were developed to provide a higher lead count, and a smaller foot print, than conventional plastic or ceramic semiconductor packages. A BGA package includes an area array of solder balls that permit the package to be surface mounted to a printed circuit board (PCB) or other electronic component.
One type of prior art BGA package 10 is illustrated in FIG. 1A. The BGA package 10 includes a substrate 12, an array of solder balls 14 on the substrate 12, and a semiconductor die 16 on the substrate 12 in electrical communication with the solder balls 14. The BGA package 10 also includes a die encapsulant 18 that encapsulates the die 16, and a wire bond encapsulant 20 that encapsulates wire bonds 22 between the die 16 and a pattern of conductors 36 on the substrate 12. In addition, the BGA package 10 includes a solder mask 24 having openings 26 on selected areas of the conductors 36 wherein the solder balls 14 are located.
Typically the substrate 12 comprises a reinforced polymer laminate material, such as bismaleimide triazine (BT), or a polyimide resin. In addition, the substrate 12 is initially a segment of a substrate panel 12P (FIG. 1B) which is similar to a lead frame used in the fabrication of conventional plastic semiconductor packages. The substrate panel 12P includes multiple substrates 12, and is used to fabricate multiple BGA packages 10. Following the fabrication process for the BGA packages 10, the substrate panel 12P is singulated into individual BGA packages 10.
The die encapsulant 18 and the wire bond encapsulant 20 can comprise a plastic material such as a Novoloc based epoxy formed using transfer molding process. The BGA package 10 is sometimes referred to as being xe2x80x9casymmetricalxe2x80x9d because the die encapsulant 18 has a larger size and volume than the wire bond encapsulant 20.
One problem with the asymmetrical BGA package 10, which is illustrated in FIGS. 1B and 1C, occurs during molding of the wire bond encapsulants 20. During fabrication of the BGA packages 10 on the substrate panel 12P, the die encapsulants 18 are initially molded to the substrate panel 12P using a first mold fixture 28 (FIG. 1B). The first mold fixture 28 includes mold cavities 30 (FIG. 1B) and associated runners (not shown) in flow communication with a source of heated, pressurized plastic. The mold cavities 30 are configured to mold the die encapsulants 18 onto the substrate panel 12P.
After molding the die encapsulants 18, the wire bond encapsulants 20 are molded to the panel 12P using a second mold fixture 32 (FIG. 1C). The second mold fixture 32 also includes mold cavities 34 (FIG. 1C) and associated runners (not shown) in flow communication with a source of heated, pressurized plastic. The mold cavities 34 are configured to mold the wire bond encapsulants 18 on the substrate panel 12P.
Because of the construction of the first mold fixture 28, a relatively high clamping pressure P1 (FIG. 1B) can be exerted on either side of the substrate panel 12P for sealing the mold cavities 30 during molding of the die encapsulants 18. However, because of the construction of the second mold fixture 32, only a relatively low clamping pressure P2. (FIG. 1B) can be exerted on one side of the panel 12P for sealing the mold cavities 34 during molding of the wire bond encapsulants 20.
The relatively low clamping pressure P2 can allow excess plastic material, or xe2x80x9cflashxe2x80x9d, to escape from the mold cavities 34 (FIG. 1C). The flash can deposit on the conductors 36 (FIG. 1A), and in the openings 26 (FIG. 1A) in the solder mask 24 (FIG. 1A). Depending on its location, the flash can adversely affect the solder balls 14, and the bonded connections between the solder balls 14 and the conductors 36.
In view of the foregoing, improved methods for controlling mold flash during fabrication of semiconductor packages are needed in the art. The present invention is directed to a method for fabricating a semiconductor package in which mold flash is contained on a selected area of the package.
In accordance with the present invention, a method for fabricating semiconductor packages, a semiconductor package fabricated using the method, and an electronic assembly that includes the package are provided.
In the illustrative embodiment, the method is used to fabricate an asymmetrical BGA semiconductor package. The package includes a substrate and a semiconductor die mounted to the substrate. Initially, the substrate is provided with a first surface having a pattern of conductors, and an array ball bonding pads. The substrate also includes an opposing second surface with a die mounting area, and a wire bonding opening between the opposing surfaces. The die is attached circuit side down to the die mounting area, and wire bonds are formed through the wire bonding opening, between die contacts on the die, and the ball bonding pads on the conductors.
Following attaching and wire bonding of the die, a die encapsulant is formed on the second surface of the substrate to encapsulate the die. The die encapsulant can be molded using a conventional mold tooling fixture having a mold cavity with a geometry corresponding to that of the die encapsulant.
Following molding of the die encapsulant, a wire bond encapsulant is molded on the first surface of the substrate to encapsulate the wire bonds. For molding the wire bond encapsulant, a mold tooling fixture includes a mold cavity, and opposing flash control cavities located on either side of the mold cavity. The flash control cavities function to collect excess encapsulant, or flash, during molding of the wire bond encapsulant. This restricts the flash to a flash area on the substrate, and prevents the flash from contaminating the ball bonding pads. In addition, the flash control cavities provide pressure relief for the pressurized molding compound within the mold cavity during molding of the wire bond encapsulant. In the illustrative embodiment the flash control cavities comprise parallel spaced grooves in the mold tooling fixture located on either side of longitudinal edges of the mold cavity.
Following the molding steps, solder balls can be bonded to the ball bonding pads to form terminal contacts for the package. Because of the absence of flash on the ball bonding pads, bonding of the solder balls and the resulting bonded connections are improved, and package reliability is improved.
The electronic assembly includes one or more packages surface mounted to a supporting substrate, such as a printed circuit board.
FIG. 1A is an enlarged schematic cross sectional view of a prior art BGA package having an asymmetrical configuration;
FIG. 1B is a schematic cross sectional view illustrating a first molding step during fabrication of the prior art BGA package;
FIG. 1C is a schematic cross sectional view illustrating a second molding step during fabrication of the prior art BGA package;
FIG. 2A is a plan view of a panel containing multiple substrates for fabricating a semiconductor package in accordance with the invention;
FIG. 2B is a bottom view of the panel;
FIG. 2C is an enlarged portion of a substrate on the panel taken along section line 2C of FIG. 2A;
FIG. 2D is a cross sectional view of the substrate taken along section line 2Dxe2x80x942D of FIG. 2C;
FIG. 2E is a cross sectional view of the substrate taken along section line 2Exe2x80x942E of FIG. 2C;
FIG. 2F is a cross sectional view of the substrate taken along section line 2Fxe2x80x942F of FIG. 2C;
FIGS. 3A-3E are schematic cross sectional views illustrating steps in a method for fabricating a semiconductor package in accordance with the invention;
FIG. 4A is an enlarged portion of FIG. 3D with parts removed illustrating a mold cavity having flash control cavities;
FIG. 4B is an enlarged plan view of the mold cavity and flash control cavities taken along line 4Bxe2x80x944B of FIG. 4A;
FIG. 4C is an enlarged portion of FIG. 4B taken along line 4C;
FIG. 4D is an enlarged portion of FIG. 3E taken along line 4D;
FIG. 4E is an enlarged portion of FIG. 3E taken along line 4E; and
FIG. 5 is a schematic plan view of an electronic assembly constructed in accordance with the invention.